The present invention relates to semiconductor devices, and more specifically, to gate cutting methods for vertical transistor devices.
As demands to reduce the dimensions of transistor devices continue, new designs and fabrication techniques to achieve a reduced device footprint are developed. Vertical-type transistors such as vertical field effect transistors (vertical FETs or VFETs) have recently been developed to achieve a reduced FET device footprint without comprising necessary FET device performance characteristics.
However, when devices that include multiple VFETs are formed, they often include an underlying metallic layer by which each of the VFETs are communicative. This underlying metallic layer often needs to be cut. However, cutting the underlying metallic layer without damaging the rest of the device is difficult.